/**
  ******************************************************************************
  * @file    dma2d_drv.h
  * @author  Product application department
  * @version V1.0
  * @date    2020.02.13
  * @brief   Header file of DMA2D DRV module.
  *
  ******************************************************************************
  */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __DMA2D_DRV_H
#define __DMA2D_DRV_H

#ifdef __cplusplus
extern "C"
{
#endif

/* Includes ------------------------------------------------------------------*/
#include "drv_reg.h"
#include "drv_gpio_def.h"


 
/*** 宏定义 *******************************************************************/


//DMA2D_CR
#define MODE_MEM2MEM				(0x00 << 16)
#define MODE_MEM2MEM_PFC		(0x01 << 16)
#define MODE_MEM2MEM_BLEND	(0x02 << 16)
#define MODE_REG2MEM				(0x03 << 16)
#define DMA2D_START					(1 << 0)
#define DMA2D_SUSP					(1 << 1)
#define DMA2D_ABORT					(1 << 2)
#define CR_TEIE							(1 << 8)
#define CR_TCIE							(1 << 9)
#define CR_TWIE							(1 << 10)
#define CR_CAECIE						(1 << 11)
#define CR_CTCIE						(1 << 12)
#define CR_CEIE							(1 << 13)
#define ALPHA_CMP_EN				(1 << 15)
#define CR_BURST_TYPE				(1 << 22)

//DMA2D_ISR
#define ISR_TEIF						(1 << 0)
#define ISR_TCIF						(1 << 1)
#define ISR_TWIF						(1 << 2)
#define ISR_CAECIF					(1 << 3)
#define ISR_CTCIF						(1 << 4)
#define ISR_CEIF						(1 << 5)

//DMA2D_IFCR
#define IFCR_CTEIF					(1 << 0)
#define IFCR_CTCIF					(1 << 1)
#define IFCR_CTWIF					(1 << 2)
#define IFCR_CCAECIF				(1 << 3)
#define IFCR_CCTCIF					(1 << 4)
#define IFCR_CCEIF					(1 << 5)

//DMA2D_FGPFCCR / DMA2D_BGPFCCR
#define PFCCR_ALPHA_MASK		(0xFF << 24)
#define PFCCR_CS_MASK				(0xFF << 8)		//CLUT size
#define PFCCR_AM_MASK				(0x3 << 16)		//alpha mode
#define PFCCR_CM_MASK				(0xF << 0)		//color mode
#define PFCCR_CCM						(1 << 4)			//CLUT color mode
#define PFCCR_START					(1 << 5)			//start the automatic loading of the CLUT

//DMA2D_OPFCCR? / DMA2D_IFCR
#define ALPHA_CMP_VAL_MASK	(0xFF << 24)

typedef enum
{
	CM_ARGB8888 = 0,
	CM_RGB888,		//1
	CM_RGB565,		//2
	CM_ARGB1555,	//3
	CM_ARGB4444,	//4
	CM_L8,				//5
	CM_AL44,			//6
	CM_AL88,			//7
	CM_L4,				//8
	CM_A8,				//9
	CM_A4,				//10
	CM_COUNT
} COLOR_MODE;

//#define DMA2D_INT_EN
#define DMA2D_DMA_BUS_TEST

extern int g_flg_dma2d_done;
extern volatile int dma_int;


extern const int c_PIX_SIZE[];

/**
  * @brief DMA2D初始定义
  */
typedef struct
{
    COLOR_MODE InFgFormat;           
    COLOR_MODE InBgFormat;
	
    COLOR_MODE OutFormat;      
   
    uint32_t InFgAddr; 
    uint32_t InBgAddr; 	
	  uint32_t OutAddr;     

    COLOR_MODE ClutFgFormat;
	  uint32_t ClutFgAddr;
	  uint32_t ClutFgSize;
	
    COLOR_MODE ClutBgFormat;
	  uint32_t ClutBgAddr;
	  uint32_t ClutBgSize; 
	
	
	  uint16_t  Width;       /**<输入图像宽度*/
	
	  uint16_t  Height;      /**<输入图像高度*/
	
  	uint32_t  InFgOffset;
		uint32_t  InBgOffset;
		
	  uint32_t  OutOffset;
	
	  uint8_t   DMA2D_INT;
	  uint8_t   DMA2D_BURST;
		
    uint8_t   EnableIE;		
		uint8_t   G_flg_dma2d_done;
		uint32_t RegARGBColor;
	
}DMA2D_InitTypeDef;

 
 
/**
  * @brief  DMA2D 常用宏常量
  *
  */


/**
  * @brief DMA2D通信状态枚举
  */
typedef enum
{
  DRV_DMA2D_STATE_RESET             = 0x00,  /**< DMA2D not yet initialized or disabled         */
  DRV_DMA2D_STATE_READY             = 0x01,  /**< DMA2D initialized and ready for use           */
  DRV_DMA2D_STATE_BUSY              = 0x02,  /**< DMA2D internal process is ongoing             */
  DRV_DMA2D_STATE_BUSY_TX           = 0x12,  /**< Data Transmission process is ongoing        */
  DRV_DMA2D_STATE_BUSY_RX           = 0x22,  /**< Data Reception process is ongoing           */
  DRV_DMA2D_STATE_TIMEOUT           = 0x03,  /**< DMA2D timeout state                           */
  DRV_DMA2D_STATE_ERROR             = 0x04,  /**< DMA2D error state                             */
}DRV_Dma2dStateTypeDef;


/**
  * @brief DMA2D状态定义
  */
typedef enum
{
  DRV_DMA2D_OK       = 0x00,
  DRV_DMA2D_ERROR    = 0x01,
  DRV_DMA2D_BUSY     = 0x02,
  DRV_DMA2D_TIMEOUT  = 0x03,
}DRV_DMA2D_StatusTypeDef;

/**
  * @}
  */

/**
  *@}
  */

/**
  *@}
  */
extern void DRV_DMA2D_SoftReset(void);
extern void DRV_DMA2D_ClutInit(uint32_t* addr, int32_t len);
extern void DRV_DMA2D_SetAlphaCmp(DMA2D_TypeDef *pdma2d,uint8_t val);
extern void DRV_DMA2D_FgClutLoad(DMA2D_TypeDef *pdma2d , DMA2D_InitTypeDef *pinit);
extern void DRV_DMA2D_BgClutLoad(DMA2D_TypeDef *pdma2d , DMA2D_InitTypeDef *pinit);
extern DRV_DMA2D_StatusTypeDef DRV_DMA2D_PfcHard(DMA2D_TypeDef *pdma2d, DMA2D_InitTypeDef *pinit);

extern void DRV_DMA2D_Reg2Mem(DMA2D_TypeDef *pdma2d, DMA2D_InitTypeDef *pinit);
extern void DRV_DMA2D_Mem2Mem(DMA2D_TypeDef *pdma2d, DMA2D_InitTypeDef *pinit);
extern DRV_DMA2D_StatusTypeDef DRV_DMA2D_BlendHard(DMA2D_TypeDef *pdma2d, DMA2D_InitTypeDef *pinit)	;

#ifdef __cplusplus
}

#endif

#endif /* __DMA2D_DRV_H */
